1. Field Of The Invention
The present invention relates to the field of semiconductor devices and more particularly to a method of design and manufacture of a device having dummy features in the active layers.
2. Prior Art
During the manufacture of semiconductor devices, numerous device structures or insulative layers are fabricated from various materials deposited on the surface of a semiconductor surface. Typically, a layer of the material from which a given structure is formed is deposited by sputter deposition, chemical vapor deposition (CVD), or other means. The layer is coated with photoresist which is patterned to form a mask. The material is then removed from exposed regions by a wet or dry etch as is well known in the art. The material may be, for example, a metal layer such as aluminum, titanium, tungsten, titanium nitride, various noble, near-noble or precious metals, as well as any combination of the foregoing or other metals; a silicide, including tungsten silicide, titanium silicide, and cobalt silicide among others; a polysilicon layer, doped or undoped; an oxide layer, doped or undoped; or a polymer layer such as polyimide, parylene, or a fluoropolymer, for example. The structure or layers formed could be, for example, various types of interconnection lines, contact or via fills, gates, word or bit lines, spacers, or insulative layers, among others. In addition to structures formed on the semiconductor substrate, various active regions, such as diffusion regions, are formed within the substrate.
As described above, after deposition of, for example, a metal layer, an etch of the layer is performed. Often, the etch is performed after a masking layer has been formed to define the desired pattern. In some cases, however, such as during a contact or via opening etchback, no masking layer is used and a blanket etchback is performed. In either case, the etch time depends on the amount of metal which is to remain on the substrate after the etch. That is, if the desired features occupy a small fraction of the surface area of the substrate, a longer etch time will be required than if the features occupy a larger percentage of the surface area. This phenomenon is known as the loading effect and is well known in the art.
The loading effect can cause various manufacturing problems. If a given layer has a small percentage of the layer remaining after the etch (i.e. most of the layer is to be etched), the required etch time is longer. The longer etch time can lead to resist punch through. This is due to the fact that, although the etch used is generally selective so that the layer etches at a faster rate than the resist, the resist does etch at some finite rate. This causes portions of the photoresist used as a mask to be etched through, which causes a portion of the feature, for example, a metal line, to be etched. The etching of the feature can cause device failure thereby reducing yields. Additionally, devices having partially etched metal lines pose a reliability hazard, as they may fail during use. In the prior art, the resist punch through problem is often overcome by leaving several individual die on a wafer completely covered with a metal layer, to increase the percentage of the wafer with metal remaining. Of course, this renders the covered die non-functional, thereby reducing the wafer yield.
The above described loading effect also affects the deposition times of subsequent layers. This can occur due to the fact that the impedance encountered during deposition is dependent upon the amount of metal remaining on the wafers. For example, a passivation layer deposited on a metal layer will have a longer deposition time when a small percentage of the metal remains, and a shorter deposition time when a large percentage of the preceding metal layer remains. The longer etch and deposition time caused by the loading effect can adversely affect throughput times of the individual processes. Additionally, the loading effect can also cause local variations in etch and deposition rates across the surface of a wafer, leading to non-uniformities.
The loading effect also adversely affects product manufacturability in fabrication facilities where several different types of devices are fabricated by a single process. For example, a particular process sequence may be used for metal 1 etch for all devices. During production, a lot of wafers of one type of device may be processed through that sequence, followed by a lot of wafers of a different device type. If the two different products have different percentage metal remaining, different etch parameters must be utilized to process the different lots. The parameters used may include gas flow rates, power, pressure, electrode gap distance, and etch time. The set of parameters used for an etch or deposition is referred to as a recipe. The requirement of different parameters means that each new product must have the etch process re-engineered so that it is optimized for that product. In addition to the additional engineering resources utilized, the requirement for different recipes for the various etch and deposition steps for each product reduces throughput as the etch or deposition recipe must be changed prior to the processing of a lot of wafers through the process.
What is needed is a method and design allowing for different types of devices to be processed through a process step utilizing the same process recipe.